Comment by tux3

To play devil's advocate, I wonder how well they handle more annoying things.

When a CMOS switches, it essentially creates a very brief short circuit between VCC and GND. That's part of normal dynamic power consumption, it's expected and entirely accounted for.

But I don't know how these cloud FPGAs could enforce that you don't violate setup and hold times all over the place. When you screw up your crossings and accidentally have a little bit of metastability, that CMOS will switch back and forth a little bit, burn some power, and settle one way or the other.

Now if you intentionally go out of your way to keep one cell metastable as long as possible while the neighbors are cold, that's going to be one hell of a localized hotspot. I wouldn't be surprised if thermal protection can't kick in fast enough.

It's just kibitzing though, I'm not particularly inclined to try with my own hardware