Comment by dlojudice

I think the core question is whether hardware-accelerated translation could be meaningfully faster than software like Rosetta 2/Prism while avoiding the full dual-ISA complexity you're describing. Rather than literally implementing both instruction sets, it might be more like an ARM chip with specialized translation units and the extended ISA features you mentioned (memory ordering, etc.).

Intel's unique position with x86 IP could make this feasible where others can't, but whether the engineering effort is worth it for what might be a short-term market advantage is debatable.