Comment by jsheard
3 months ago
My understanding is that Rosetta sidesteps a bunch of tricky memory model issues by using non-standard hardware extensions only present in Apple Silicon, so even if Apple did share Rosetta, which they certainly won't, it wouldn't work properly on Valves hardware anyway.
It's not only present in Apple Silicon, it's just not required by the ARM standard. Fujitsu also has an ARM64 CPU with TSO.
Nice article on this topic: https://lwn.net/Articles/970907/
There are a bunch of undocumented flags and instructions beyond TSO.
Trust me on this one?
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There are also RISC-V designs with TSO. If you are targeting x86 workloads, it makes sense to have a per thread TSO mode.
yeah that is correct. The m series chips can turn on total store ordering memory model solely for Rosetta. There's also some hardware extensions to arm to support x86 condition codes in the hardware because it's way more instruction efficient that way.
The latter is now an optional feature in the mainstream Arm ISA now (FEAT_FlagM and FEAT_FlagM2). Similarly the “alternate floating point mode” that Apple uses to match nuances of x86 FP semantics is a standard architectural feature as well. The TSO option though is Apples own thing.
If you mean FEAT_FlagM, that's standard in ARMv8.4. (There's also FlagM2 and AFP that are optional.)
The JavaScript instruction is cooler though.
https://developer.arm.com/documentation/dui0801/g/A64-Floati...
RISC is dead; long live RISC