Comment by astrange
3 months ago
It's not only present in Apple Silicon, it's just not required by the ARM standard. Fujitsu also has an ARM64 CPU with TSO.
3 months ago
It's not only present in Apple Silicon, it's just not required by the ARM standard. Fujitsu also has an ARM64 CPU with TSO.
Nice article on this topic: https://lwn.net/Articles/970907/
There are a bunch of undocumented flags and instructions beyond TSO.
Trust me on this one?
https://dougallj.wordpress.com/2022/11/09/why-is-rosetta-2-f...
> Apple M1 has an undocumented extension that, when enabled, ensures instructions like ADDS, SUBS and CMP compute PF and AF and store them as bits 26 and 27 of NZCV respectively, providing accurate emulation with no performance penalty.
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There are also RISC-V designs with TSO. If you are targeting x86 workloads, it makes sense to have a per thread TSO mode.