Comment by elevation
2 hours ago
Why couldn't a company committed to mask fabrication and wafer fabrication, in concept, perform these steps daily, or several times daily? Multiple prototype designs could be grouped together so multiple customers can realize a new design instance in the same iteration.
With an appropriate debug core in the same wafer, designers who'd completed a tape-out could connect to their chip well enough to repeat their design-verification tests on this real hardware, remotely even (no need to physically handle the device 'til you're certain it's working.) Once satisfied, customers could promote their design to be bonded out for installation into their PCB.
"Sure thing boss, we'll add an extra USART core to this afternoon's tape out."
Because you are dealing with the physical world where those different designs have different requirements that can conflict. It’s like saying all software is basically the same, why don’t you just abstract it all and run it on these Raspberry Pi’s.
You can do that, but it’s going to turn out poorly.
The wafer manufacturing process takes weeks to months after a tape out.
Accelerating this process sounds like a good focus for an SBIR (small business innovation research) RFP.
A fab is not a small business!
Part of the delay is really just commercial. Fabs are optimized for utilization - throughput, not latency. A fab operator will prefer to queue up a load of work with as few gaps as possible, and your shuttle service run has to fit in one of the gaps. If you're NVIDIA and you've already booked the fab, there might not be so much delay. But not zero.
Nice little backgrounder: https://siliconmasters.co/blogs/our-blog/how-photomasks-for-...
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I sort of expected this to happen with tightly coupled customer-customizable chiplets inside a single package, instead. But it seems that packaging is also better left to Intel and AMD, I guess.
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