Comment by DoctorOetker

> When asked about the Pi Zero 2W, Eben said the substrate supply is constrained—basically, so many AI chips are being made that even older chips using older process nodes have to fight for the actual silicon wafers to use to make the chips.

I keep hearing voices invalidate each other, is the bottleneck the raw silicon substrate, or fab capacity?

What purity levels are required for say Pi Zero 2W?

The volume of monocrystalline silicon used in solar panels is orders of magnitude greater than the volume used in IC's / RAM production.

Is the actual bottleneck 11N + grade silicon wafers while 6N to 9N grade used in solar panels remains unaffected?