Comment by torginus
2 days ago
With regards to RAM price I never understood the following: A 16GB RAM stick has 16*8=128 billion bits, with 1 transistor per bit, thats still 128B, yet its supposed to cost like $60 before the price hikes? In contrast, a 5090 GPU was $2000 (true it has RAM, but you're paying for the GPU ASIC really, I guess the rest of the GPU was less than $500), it had 93B transistors.
GPU transistors are smaller due to the more advanced process node (cost per transistor metrics aren't really clear, if they improve on advanced node or not, but I'd say they get cheaper as they get smaller, as technology costs are amortized).
I'm sure both RAM and logic use a process that is quite similar in both inputs and manufacturing steps. So while RAM is a commodity product, this insane price difference didn't make any sense.
So I guess when those fundamental inputs become a constraint, it would make sense for $/transistor move closer for both, which is a massive hike for RAM.
Chip fabrication processes are not fungible: GPUs and CPUs might be made on roughly the same process, but DRAM is not (flash is a different process again, as is power electronics, analog electronics, MEMS, etc. And even within those broader categories there are different variations). While there are some overlaps in machines and techniques, a fab set up for one cannot generally switch to the other, and the economics of each process can also be drastically different.
You're not the first person to say so (and I don't mean to dispute it), but I have never been able to find a clear answer for /why/ those processes are incompatible.
Is it built in different silicon, is it physical steps that's incompatible (ie its actually incompatible), is it different physical preparations that needs to be made (making it economically infeasible to combine)
I cannot help but wonder, even if the answer doesn't change anything in my life.
To add to the other comments…
At a very abstract level, when you're manufacturing DRAM you need to manufacture a lot of circuit elements that have HIGH capacitance, since a DRAM cell is basically a capacitor and the higher its capacitance the less frequently it needs to be refreshed.
On the other hand, when manufacturing logic (CPU/GPU/ASIC) you want to minimize the capacitance of almost all circuit elements, since capacitance introduces delay and switching energy cost.
Nearly everything about the manufacturing processes for DRAM and logic is optimized around this fundamentally incompatible figure of merit.
I worked on the development of Intel's eDRAM process, which was used to integrate DRAM into the CPU/GPU die for Iris Pro embedded graphics from 2013-23. https://ieeexplore.ieee.org/document/6576667/
https://www.reddit.com/r/Semiconductors/comments/r1dqmw/how_...
A Reddit user explains a bit here.
Medium ELI5 answer: each company and to a great extent each individual fab has a slightly different recipe, which is known as a "process node". This defines all the fabrication steps, every individual layer and its chemical/physical processing.
This in turn affects the electrical properties: parasitic resistance/capacitance, gate dielectric properties and so on. The dielectric in particular is critically different between DRAM and regular CMOS, because DRAM needs to minimise leakage (as that determines how long the memory lasts between refresh cycles).
Regular factories will retool somewhat between jobs. Because it is quite difficult to finetune a silicon process node, it is more common that a fab will set up for a particular node and then switch to "do not touch or change anything under any circumstances", as doing so may wreck yields.
("different substrate entirely" does exist: that's GaN, for power transistors in phone chargers, and SiC, for even higher power transistors.)
The physical structure is completely different. Just compare DRAM ([0]) with compute ([1]). As a result, the production process is completely different.
If you want to know more, the Asianometry youtube channel has some fairly good deep dives, such as [2] going through a decent bunch of the 45nm production process, or [3] doing the same for (early) DRAM.
[0]: https://www.youtube.com/watch?v=Bln-v9LmZ3E
[1]: https://i1.wp.com/semiengineering.com/wp-content/uploads/201...
[2]: https://www.youtube.com/watch?v=zUgy29h0alM
[3]: https://www.youtube.com/watch?v=uPualBNf1nM
To expand a little on this: a chip fabrication process is a series of steps from incoming bare wafers to finished chips (potentially multiple wafers get combined into a finished chip, as well). To build up the physical structure of the chip, there are a series of steps where different materials are deposited or grown on the surface, masked through photolithography, and removed in order to shape the structure of the chip layer by layer. Each of these depends on not just what that layer itself requires (material, thickness, resolution), but also on the layers around it, because these steps are not independent: a lot of process design is in finding a way to construct a given chip that means each step is compatible with the others.
What's more, the configuration and flow of the machines used for each step are quite sensitive: you cannot in general just stand up another fab with the same machines, apply the same settings, and hit go on a new chip design and expect any yield: you need to dial in each step, certainly for each process, and likely for each design. This makes switching things around more difficult as well.
So, while in general a fab will have certain common features: spin coaters, photolithography machines, vapor deposition chambers, ovens, etc, the number and specification of each one will vary based on the process, and a production fab will generally not want to change their process drastically, or even to swap between different designs too often.
from my basic understanding, memory is much easier to produce then logic chips like GPUs and CPUs, they don't need that many photolithographic layers. while it could be possible to produce memory in fabs for CPUs (though not really desirable in regard to costs) the other way round is more difficult
DRAM is highly regular and relies on a 1T1C (one transistor, one capacitor) structure. Because those tiny capacitors naturally leak charge, the adjacent transistors must be optimized for ultra-low leakage. That requires thicker gate oxides and higher threshold voltages which makes them slow. Furthermore, digging those deep trench or stacked vertical capacitors requires highly specialized, high-aspect-ratio etching and deposition tools. Also, for DRAM the backend wiring is completely different; DRAM is a giant, uniform grid that only needs about 3–5 metal layers to keep costs rock-bottom while modern logic is highly irregular and complex, requiring 12–16+ metal layers.
Logic processes (CPUs/GPUs), on the other hand, are optimized for raw switching speed. They use thin gate oxides and low threshold voltages, which leak like a sieve. This is fine for a fast processor, but it would wipe out a DRAM cell's charge almost instantly.
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RAM is literally copy-paste of the same circuit over and over, you're trying to compare cost to produce million AK-47 with 1 carrier
and cost per transistor stopped decreasing at ~20-30nm, now small nodes are targetting energy efficiency (and thus performance, since heat is the main limiter)
RAM is a commodity. It has much less moat to prevent competitions. When the rams flood the market that's when the bubble ends, until the next cycle arrives. Processors are much harder to design and commoditize.
On top of everything said, 5090 die size is 10x than typical DDR5 die size. One RAM module is 8-16 dies, so you do get more silicon in the end, but larger dies are extremely expensive to produce due to sharply decreasing yields.
The thing that defines performance of DRAM is AFAIK the capacitor of the bit cells and not the transistor driving it. And also AFAIK the process to create those capacitors is quite unique to DRAM, so you can't just go and use a "logic" process unchanged and produce DRAMs.
> So while RAM is a commodity product, this insane price difference didn't make any sense.
Supply and demand coupled with the fact that a RAM fab can't (trivially) output compute chips, and vice versa, a compute fab can't output RAM. It's two completely different supply chains.
Consider that the R&D cost of the GPU (>>> RAM) must be amortized across total units sold (<<< RAM).
newer process node are smaller but very expensive compared to mature ones, each wafer from TSMC latest process is costly and with lower yield due to GPU large die size (+700mm2 compared to around 60mm2 per DRAM die)
Why would you expect smaller transistors to be cheaper?
Because you are paying for silicon, and processes, not transistors. Wafers have a certain cost, and litographic processes can illuminate a certain X mm2 of dies in an hour. If a transistor gets smaller, more of them fit in a certain area.
Granted the machines that make them become more expensive, but that's capital expenditure, which gets amortized as time goes on.
So there are two forces here working against each other.
You are not paying for silicon, lol. The cost of a chip is many, many orders of magnitude more than the raw material cost.
That is what Moore's Law said.
Not really a law though.
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A GPU Transistor is a lot more complicated than a RAM transistor and the size of these are quite different too. Bleeding edge vs. a known process with know machines and written off machines.
Also you calculate in the machine cost and R&D.
RAM hiked because the demand spiked and these companies are now in power. Before apple and other companies told them the prices and had hardly any money for investment.