Comment by cduzz

DRAM is highly regular and relies on a 1T1C (one transistor, one capacitor) structure. Because those tiny capacitors naturally leak charge, the adjacent transistors must be optimized for ultra-low leakage. That requires thicker gate oxides and higher threshold voltages which makes them slow. Furthermore, digging those deep trench or stacked vertical capacitors requires highly specialized, high-aspect-ratio etching and deposition tools. Also, for DRAM the backend wiring is completely different; DRAM is a giant, uniform grid that only needs about 3–5 metal layers to keep costs rock-bottom while modern logic is highly irregular and complex, requiring 12–16+ metal layers.

Logic processes (CPUs/GPUs), on the other hand, are optimized for raw switching speed. They use thin gate oxides and low threshold voltages, which leak like a sieve. This is fine for a fast processor, but it would wipe out a DRAM cell's charge almost instantly.