Comment by zephen
2 days ago
> RISC-V is... fine
Exactly.
> It satisfies my two requirements for an ISA as a hobby CPU designer...
You probably have some unstated requirements as well, such as available toolchains and "vetted well enough to actually be able to run code."
Risc-V now occupies the Schelling point for people who, for whatever reason (rent-seeking and security top the list) want to leave the x86 and Arm ecosystems.
Luke is too modest. Something in the region of 5 million chips containing his hobby CPU have shipped since launch on August 8, 2024.
Are we talking about rp2350 ? Because the rp2350 can be config as pure arm soc.
In fact, if we are talking about successfull riscv soc, RISC-V esp32 may have better chance
Could you share a link or more details? What is this hobby CPU project?
I think the GP is talking about the Hazard3 [1] core. This is one of the CPU cores besides the ARM M33 instantiated on the RP2350 µC [2]. See this article from Luke Wren (Wren6991) back when the RP2350 came out [3].
[1] https://github.com/Wren6991/Hazard3
[2] https://www.raspberrypi.com/products/rp2350/
[3] https://www.raspberrypi.com/news/risc-v-on-raspberry-pi-pico...
4 replies →
Luke Wren works at Raspberry Pi and designed the Hazard3 CPU core that is in the RP2350 chip.
They did explicitly specify:
> 1. Supported in mainline LLVM and GCC.
Which pretty well encapsulates the ecosystem requirements.