I think the GP is talking about the Hazard3 [1] core. This is one of the CPU cores besides the ARM M33 instantiated on the RP2350 µC [2]. See this article from Luke Wren (Wren6991) back when the RP2350 came out [3].
What I find interesting is that RP2350 is designed as "one or the other", no way to use ARM and RISC-V concurrently, and has fuses that can kill ARM M33 cores outright.
Makes me wonder if an "ARM cores fused off, RISC-V only, no ARM fees" SKU is possible.
I think the GP is talking about the Hazard3 [1] core. This is one of the CPU cores besides the ARM M33 instantiated on the RP2350 µC [2]. See this article from Luke Wren (Wren6991) back when the RP2350 came out [3].
[1] https://github.com/Wren6991/Hazard3
[2] https://www.raspberrypi.com/products/rp2350/
[3] https://www.raspberrypi.com/news/risc-v-on-raspberry-pi-pico...
What I find interesting is that RP2350 is designed as "one or the other", no way to use ARM and RISC-V concurrently, and has fuses that can kill ARM M33 cores outright.
Makes me wonder if an "ARM cores fused off, RISC-V only, no ARM fees" SKU is possible.
You can choose Arm in one pair and RISC-V in the other pair if you want.
Several of the peripherals in the RP2350 are also ARM IP.
Thank you!
Luke Wren works at Raspberry Pi and designed the Hazard3 CPU core that is in the RP2350 chip.