Comment by jack_h
1 day ago
> What does a cheap microcontroller core need? Let's inspect what they are used for. Typical use cases are to interface with and quickly reconfigure hardware blocks in a larger chip, eg in an MP3 player, an SD card, or a USB stick. The hard work is done by custom IP and the CPU core is just there to occasionally prod a register or configure something.
This is not the only reason to use a microcontroller or 75% of microcontroller vendor (e.g. STM) offerings would have no customers. Not everyone has custom IP that does all the work either, that’s actually fairly rare. It’s odd to pigeonhole microcontrollers like this just to go on a fairly lengthy rant about interrupt latency as if that somehow makes RISC-V unsuitable to what is an incredibly diverse application space. Maybe the rest of their post has better arguments, but I’m not impressed enough by the first one to keep reading.
This is a "microcontroller core", not a "microcontroller".
We're talking "deep embedded" applications - where an ASIC is designed for a very specific purpose, and that design just so happens to call for a programmable CPU core to be included in it.
This is the kind of design that lives in your keyboard, your mouse, your USB stick, your USB hub, your HDD, your SSD, your eMMC chip, your memory card and more. Remember: you're never more than 3 meters away from an 8051 core.
I do agree that most of this piece is nitpicking - poking at ultra low level things that are largely irrelevant to the tried and true "deep embedded" exercise of Just Ship It.
No one really gives a shit if an operation takes one instructions or two, or which instruction sets are consistently present in different cores. What "deep embedded" people give a shit about is not having to work with ancient 8051 tooling and 8 bit ALUs and memory banked 64kb spaces while writing code for the one core they happen to actually have. And RISC-V got that. The piece actually agrees with that sentiment.
Å microcontroller needs a microcontroller core.
EDIT: Leaving that Å in. For some reason, iOS on iPad is obsessed with autocorrecting "A" to "Å" even when using the English keyboard. It's driving me nuts.
You can add a correction going the other way and it may fix the problem (it did for me for a similar problem, anyway) in Settings -> General -> Keyboard -> Text Replacement. Try replacing “Å” with “A”, or “A” with “A”, and see if that helps.
That autocorrect business would be a great modern technology prank to do to someome on purpose.
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Isn't there a setting to turn auto-correct off?
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Does the 'Å' pop up if you long press 'A'?
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By volume, I would expect the majority of microcontroller silicon shipped to be these kinds of deeply embedded cores. They even show up in chips called “microcontrollers.”
I thought cortex-m0 was taking over that slice of the pie.
I thought so, too. The Cortex M0+ is quite nice. RPi Pico RP2040 (original) https://pip-assets.raspberrypi.com/categories/610-raspberry-... uses them, and with the RPi on-chip math help (clever stuff) it's quite the joy for your toaster or microwave oven project. RV32EC is 'ok' but the weirdly reduced register set to save a few dozen transistors seems like out-of-control hardware guys without any software supervision - the bane of this industry.
Now-a-days, I actively avoid RVxxx Zwhatever because those guys had their chance and seemed to have learned nothing from the IBM 360: SOFTWARE is what ultimately matters, as long as you don't have ridiculously expensive chips, keep the ABI consistent!
And, ARM learned from M0 and quickly came out with the M0+ --- which SHOULD be the 8051 killer (no offense to my friend John Wharton (RIP), 8051 designer https://en.wikipedia.org/wiki/John_Harrison_Wharton): M0+ is a lower-power, more efficient redesign of M0, 2-stage pipeline, Harvard bus, and optional features (MPU, MTB, fast I/O) that M0 lacks. The RPi Pico has all of these optional features except the MTB (Micro Trace Buffer), but does have 4 breakpoints / 2 watchpoints per core, 8 memory regions, single-cycle I/O port access, 30% less power than M0, and 12% less die area, 32x32 single-cycle multiply, Thumb-2: "32‑bit Performance at 8‑bit Cost" https://documentation-service.arm.com/static/60411750ee93794...
Maybe certain Chinese RV32E variants will get uber popular (WCH CH32V003 under a dime in quantity https://wch-ic.com/products/CH32V003.html ). Maybe.
Not really. Before RISC-V, the low end was held firmly by 8051, and at the high end, it was a fight between Xtensa, ARC, M0, and "others", be that custom ISAs or something like legally distinct MIPS.
Now, both ends have RISC-V seeping into them.
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