Comment by wren6991

> C -> "ZcfZcdZca" just by itself is insanity

Separating the float load/stores from the rest of the compressed ISA is insanity? Why?

> Now I can't make vendor-independent RISC-V code

I think this is what RVA23 is for. Any system running shrinkwrapped binaries is going to have vanilla RVC.

I agree there is some insane stuff going on in RISC-V. Like when the double-trap spec was in public review I popped my head in to say "hi, this seems to break all existing code that uses nested interrupts because the condition is overly broad" and the spec maintainer said words to the effect of "yes, it's supposed to do that."

This is not that weird, though? Float load/store should never really have been included in the C extension, but we can't revise the C extension. So, define an extension for "C: the good parts", aka Zca, and separate extensions for float load/store (two of them because F and D are separate). Ideally we wouldn't have made the mistake in the first place, but what would have been a better way to redact it?