Comment by thefourthchime
7 hours ago
This smells somewhat legitimate and somewhat BS. The architecture itself looks impressive — TSMC 3nm, a 4+ GHz prime core, tons of cache, and a very wide execution engine. And the claimed Geekbench numbers — around *3,945 single-core and 15,221 multi-core* — are especially impressive, if not a little suspicious.
But it’s sorta like, let’s throw everything against the wall and get the biggest number we can. Do they show sustained performance over ten minutes? What’s the power draw when it’s doing 15K? What happens when you put it in an actual phone?
This was done in a cold room. It seems more like a proof of concept for what they could do than something that could actually ship in a phone and sustain those numbers.
Were I to guess
> The biggest cores on the the Xring O3 are the C1-Ultra. C1-Ultra really powerful cores. They support SME2 (Scalable Matrix Extension 2) for matrix/AI acceleration, SVE2 for data parallelism (SIMD).
This is where the magic is happening (I believe). They have these ultra cores with additional extensions which they are pinning the benchmarks to.
Realistically, that sort of thing isn't useful as non-homogeneous architectures really suck for an application or OS to deal with.
> Realistically, that sort of thing isn't useful as non-homogeneous architectures really suck for an application or OS to deal with.
I agree that if each core doesn't "support" the full ISA it's a huge pain (the one generation of Intel AVX-512-but-not parts were incredible), but that hasn't been common in years. Usually (and in this case, according to my reading) the small cores get a horrible slow/decoder-emulated implementation of every instruction, so that if you schedule on the "wrong" core you don't trap but just run really slowly instead.
Otherwise, heterogeneous architectures are the present and future of mobile and consumer desktops and have been for years. Desktop OSes are getting better and mobile OSes are just fine at scheduling across different core families (the higher level of abstraction everyone complains about in mobile apps actually helps a lot here).
didn't intel discontinue heterogeneous (laptop?) chips recently
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All 10 cores support the same extensions. It’s silly to implement an SoC any other way, and it’s been a decade since someone has last made that mistake.
It will be interesting to find out the details. From the block diagram, the core only issues 10 instructions per cycle, so not especially wide. Maybe the performance will be worse once in a real phone in real thermal conditions, but if that's true, it could make for a very interesting laptop or desktop chip. Time will tell.
The C1-ultra has a decode of 10 instructions but can issue up to 23 uop per cycle, that’s a good bit wider than any other CPU. In particular, I believe it’s the first CPU to have a 4th load pipeline.
Doesn’t matter. Details don’t matter. Look at the top comment thread: just politics and no discussion of the tech.
It is just the same as MediaTek Dimensity 9500. They managed 4000+ point in lab, but real world it was much closer to 3300.
It is still not a bad results though. And we are about to see MediaTek Dimensity 9600 based on ARM C2-Ultra.
> But it’s sorta like, let’s throw everything against the wall and get the biggest number we can.
From what I recall reading, the impressive performance of Apple mobile CPUs is partly attributable to throwing more silicon area at the problem while not being as cost sensitive (no need to share margin with SoC vendor)