{"id":49704597,"user":"mathisfun123","time":1789422483,"time_ago":"15 hours ago","type":"comment","content":"

not all architectures have atomic cas","comments":[{"id":49705528,"user":"loeg","time":1789427450,"time_ago":"14 hours ago","type":"comment","content":"

Real architectures you'd run more than a single thread on? Such as?","comments":[{"id":49706543,"user":"tom_","time":1789435289,"time_ago":"12 hours ago","type":"comment","content":"

Quad core ARMv8-A, e.g., Nintendo Switch.","comments":[{"id":49708168,"user":"loeg","time":1789450750,"time_ago":"7 hours ago","type":"comment","content":"

ARMv8-A has atomic CAS, unless this is some silly definition thing where it's "a system that has the behavior of atomic CAS but is named something else."","comments":[{"id":49710818,"user":"tom_","time":1789471265,"time_ago":"2 hours ago","type":"comment","content":"

Maybe that's the trap I'm falling into? From memory it doesn't have any actually atomic operations, only an ll/sc sort of mechanism - which I've never really thought of as an atomic operation?

Though it's true you can end up with the same end result, in that you can just keep trying the operation until you accidentally do a read-modify-write that's ended up - well, "atomic" is a valid way to describe it.

So maybe it is good enough to count, though personally I'm still not quite convinced.","comments":[],"comments_count":0,"level":3,"url":"item?id=49710818"},{"id":49709385,"user":"monster_truck","time":1789460515,"time_ago":"4 hours ago","type":"comment","content":"

I don't think that came until 8.1","comments":[],"comments_count":0,"level":3,"url":"item?id=49709385"}],"comments_count":2,"level":2,"url":"item?id=49708168"}],"comments_count":3,"level":1,"url":"item?id=49706543"}],"comments_count":4,"level":0,"url":"item?id=49705528"}],"comments_count":5,"url":"item?id=49704597"}

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