Comment by wmf
5 hours ago
The EDA tools that are used to design chips do not support diagonal wires so that kind of rules out hexagonal grids. With only horizontal and vertical wires you end up with rectangular/square grids or rings.
5 hours ago
The EDA tools that are used to design chips do not support diagonal wires so that kind of rules out hexagonal grids. With only horizontal and vertical wires you end up with rectangular/square grids or rings.
Do you need diagonal wires for a topological hexagonal tiling?
Wouldn't a rectangular brick layout be topologically a hexagonal tiling
If that is so, would it be entirely to decrease search space for layout algorithms? I believe there isn't anything in the fabrication process that couldn't model diagonals.
I could see that square packing is more simple, but by shifting elements per row I don't see why it couldn't propagate at odd angles.
That's also my assumption. Place and route has to work out an NP hard problem on billions of wires.
Are the next generation of Cerebras chips designed by the current generation? Maybe it won't be recognizable as a particular layout but rather a chaotic but functional vibe layout.