Comment by kristianp
12 years ago
"The ISA being RISC or CISC seems irrelevant.".
I thought these were all RISC processors when you get past the instruction decoder.
12 years ago
"The ISA being RISC or CISC seems irrelevant.".
I thought these were all RISC processors when you get past the instruction decoder.
Not really. Both Intel and AMD do weird non-RISCy things beyond the decode stage.
The original difference between RISC and CISC was that RISC eschewed arithmetic+memory-operations in the same instruction. Both Intel and AMD processors violate this commandment. Instead their decomposition of instructions into uops is based more on the more pragmatic notion of choosing uops that are easy to pipeline and execute out of order.
It depends on what you consider RISC to be. The ARMs in that list decode instructions into uops too. The only CPU in that list that's probably "pure RISC", in the sense of the ISA instructions themselves being the uops, is the MIPS.
I wouldn't call X86 RISC. Granted, RISC doesn't have a clear definition anymore these days and is more or less a marketing buzzword.
I think kristianp's point is that current x86 implementations are simply an x86 instruction decoder/emulator running on a very-RISC microcoded machine.
Which is how a lot of mainframes were implemented in the 60s/70s (e.g. KL-10).
Which still leaves the question of the cost of the instruction decoder.
It's a balancing act.
Power consumption by the instruction decoder vs the power consumption of additional cache&memory bandwidth.
It's amusing that despite the complaints towards X86 in the 90's nowadays it's actually a really good instruction packing format (though it became really sensible only after AMD64).
The article explicitly addresses that the claim is that it matters for tiny processoors of 1-2 mm2 die size, but for the processor power commonly used in phones or such, that particular cost is insignificant.